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M41T60
Serial access real-time clock
Features summary

Counters for seconds, minutes, hours, day, date, month, years, and century 32kHz crystal oscillator integrating load capacitance and high crystal series resistance operation Oscillator stop detection monitors clock operation Serial interface supports I2C bus (400kHz) 350nA timekeeping current @ 3V Low operating current of 35A (@400KHz) Timekeeping down to 1.0V 1.3V to 4.4V I2C bus operating voltage Software clock calibration to compensate deviation of crystal due to temperature Software programmable output (OUT) Operating temperature of -40 to 85C Automatic leap year compensation Lead-free 16-pin QFN package Li ION rechargeable operation
AI11107

QFN16 (Q) 3mm x 3mm
32KHz Crystal + QFN16 vs. VSOJ20
VSOJ20 (47.6mm2)
2 GND Plane Guard Ring (21.5mm )
1
XI XO
SMT CRYSTAL
2 3 4
ST QFN16
July 2006
Rev 11
1/24
www.st.com 24
Contents
M41T60
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 2.3
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 3.4 3.5 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 5 6 7 8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M41T60
Summary description
1
Summary description
The M41T60 is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal controlled). Eight registers are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a twoline bi-directional bus. The built-in address register is increased automatically after each WRITE or READ data byte. The eight clock address locations contain the century, year, month, date, day, hour, minute, and second; in 24-hour BCD format. Corrections for 28-, 29- (leap year), 30-, and 31-day months are made automatically. The M41T60 is supplied in 16-lead QFN package. Figure 1. Logic diagram
VCC
XI XO SCL SDA M41T60 FT(1) OFIRQ/OUT(1)
VSS
AI08869
Note:
1
Open drain Table 1. Signal names
XI XO FT SDA SCL OFIRQ/OUT VCC VSS Oscillator Input Oscillator Output Frequency Test Output (Open Drain) Serial Data Address Input / Output Serial Clock Oscillator Fail Interrupt/OUT Output (Open Drain) Supply Voltage Ground
Figure 2.
16-pin QFN connections
NC NC VCC NC
16 XI XO VSS FT
(1)
15
14
13 12 11 10 9 NC OFIRQ/OUT SCL SDA
(1)
1 2 3 4 5
VSS
6
NC
7
NC
8
NC
AI08870
3/24
Summary description Figure 3. Block diagram
FT (1) FT OUT OFIE OSCILLATOR FAIL DETECT SECONDS MINUTES HOURS VCC VSS CONTROL LOGIC DAY DATE CENTURY/ MONTH SERIAL BUS INTERFACE YEAR ADDRESS REGISTER CALIBRATION
M41T60
(1) OFIRQ/OUT
1 Hz XI OSCILLATOR 32.768 kHz XO DIVIDER
SCL
SDA
AI08871
Note:
1
Open drain output. Figure 4. Hardware hookup for SuperCapTM back-up operation
VCC
M41T60 VCC XI XO VSS (1) OFIRQ/OUT (1) FT SCL SDA VCC Port Port
MCU
Serial Clock Line Serial Data Line
AI10476b
Note:
1
Open drain output.
4/24
M41T60
Operation
2
Operation
The M41T60 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. 2. 3. 4. 5. 6. 7. 8. Seconds Register Minutes Register Hours Register Day Register Date Register Century/Month Register Years Register Calibration Register
2.1
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from High to Low, while the clock is High, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.
5/24
Operation
M41T60
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the message is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves".
2.1.5
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Figure 5. Serial bus data transfer sequence
6/24
M41T60 Figure 6. Acknowledgement sequence
Operation
2.2
READ mode
In this mode, the master reads the M41T60 slave after setting the slave address (see Figure 7). Following the WRITE Mode Control Bit (R/W = 0) and the Acknowledge Bit, the word address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ Mode Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only increased on reception of an Acknowledge Bit. The M41T60 slave transmitter will now place the data byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is increased to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (0h to 6h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (7h). An alternate READ Mode may also be implemented, whereby the master reads the M41T60 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9 on page 9).
7/24
Operation
M41T60
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is shown in Figure 10 on page 9. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is increased to the next address location on the reception of an acknowledge clock. The M41T60 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte. Figure 7. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 8.
READ mode sequence
START START R/W R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An)
S
DATA n
DATA n+1
ACK
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS
DATA n+X
P
AI00899
8/24
NO ACK
STOP
ACK
M41T60 Figure 9. Alternate READ mode sequence
START
Operation
BUS ACTIVITY: MASTER SDA LINE
S ACK
DATA n ACK
DATA n+1 ACK ACK
DATA n+X
P NO ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00895
Figure 10. WRITE mode sequence
START
STOP
R/W
BUS ACTIVITY: MASTER
R/W
SDA LINE
S
WORD ADDRESS (An)
ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
ACK
STOP
9/24
Clock operation
M41T60
3
Clock operation
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768KHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The eight-byte Clock Register (see Table 2 on page 12) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, Minutes, and Hours are contained within the first three registers. Bits D6 and D7 of Clock Register 05h (Century/Month Register) contain the CENTURY Bit 0 (CB0) and the CENTURY Bit 1 (CB1). See Table 3 on page 14 for additional explanation. Bits D0 through D2 of Register 03h contain the Day (day of the week). Registers 04h, 05h, and 06h contain the Date (day of the month), Century/Month, and Years. the eighth clock register is the Calibration Register (this is described in the Clock Calibration section). Bit D7 of Register 00h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0,' the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST Bit to a '1,' then immediately reset the ST Bit to '0.' This provides an additional "kick-start" to the oscillator circuit. Bit D7 of Register 01h contains the Oscillator Fail Interrupt Enable Bit (OFIE - see the description in the Oscillator Fail Detection section).
Note:
A WRITE to ANY location within the first seven bytes of the clock register (0h-6h), including the OFIE and ST Bit, will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The seven Clock Registers may be read one byte at a time, or in a sequential block. The Calibration Register (Address location 7h) may be accessed independently. Provision has been made to ensure that a clock update does not occur while any of the clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. this will prevent a transition of data during the READ.
3.1
Calibrating the clock
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. The accuracy of the clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. The M41T60 oscillator is designed for use with a 6pF crystal load capacitance. When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 11 on page 12). The M41T60 design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 13. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Calibration Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower-order bits (D4-D0) in the Calibration Register 07h.
10/24
M41T60
Clock operation These bits can be set to represent any value between 0 and 31 in binary format. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64-minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. That is, +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per day which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T60 may require:
The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note 934, "TIMEKEEPER(R) CALIBRATION." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the Frequency Test (FT) pin. The FT pin will toggle at 512Hz when the ST Bit is set to '0,' and the OUT Bit and FT Bit are set to '1.' Any measured deviation from the 512Hz frequency indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction.
Note:
Setting or changing the Calibration Byte does not affect the Frequency Test output frequency. the FT pin is an open drain pin which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time.
11/24
Clock operation
M41T60
Table 2. Register map
Data Address D7 0 1 2 3 4 5 6 7

D6
D5 10 Seconds 10 Minutes
D4
D3
D2
D1
D0
Function/Range BCD Format Seconds Minutes Hours Day Date 00-59 00-59 00-23 01-07 01-31
ST OFIE 0 0 0 CB1 0 0 0 CB0
Seconds Minutes Hours 0 Day Date Month Years Calibration
10 Hours 0 0 10 Date 0 10 M.
Century/Month 0-3/01-12 Year Calibration 00-99
10 Years OUT FT S
0 = Must be set to '0.' CB0, CB1 = Century Bits FT = Frequency Test Bits OFIE = Oscillator Fail Interrupt Enable Bit OUT = Output level S = Sign Bit ST = STOP Bit
Figure 11. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F
2 2 K = -0.036 ppm/C 0.006 ppm/C
TO = 25C 5C
Temperature C
AI07888
12/24
M41T60 Figure 12. Calibration waveform
Clock operation
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
3.2
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle leap years correctly. See Table 3 on page 14 for additional explanation.
3.3
Output driver pin
When the OFIE Bit is not set to generate an interrupt, the OFIRQ/OUT pin becomes an output driver that reflects the contents of D7 of the Calibration Register. In other words, when D7 (OUT Bit) is a '0,' then the OFIRQ/OUT pin will be driven low.
Note:
The OFIRQ/OUT pin is an open drain which requires an external pull-up resistor.
3.4
Oscillator stop detection
In the event that the oscillator has either stopped, or was stopped for some period of time, and if the Oscillator Fail Interrupt Enable (OFIE) Bit is set to a '1,' an interrupt will be generated. This interrupt can be used to judge the validity of the clock and date data. The interrupt will be active any time the oscillator stops while VCC is 1.0V. The following conditions will cause the OFIRQ pin to be active:

the ST Bit is set to '1.' external interference or removal of the crystal.
The Oscillator Fail Interrupt (OFIRQ) will remain active until the OFIE Bit is reset to '0,' or the oscillator restarts. The oscillator must start and have run for at least 4 seconds before attempting to set the OFIE Bit to '1.'
13/24
Clock operation
M41T60
3.5
Initial power-on defaults
Upon initial application of power to the device, the OUT Bit will be set to a '1,' while the ST, OFIE, and FT Bits will be set to '0.' All other Register bits will initially power-on in a random state. Table 3. Century Bits Examples
CB0 0 0 1 1 CB1 0 1 0 1 Leap Year? Yes No No No Example(1) 2000 2100 2200 2300
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
14/24
M41T60
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings
Symbol TSTG VCC TSLD(3) VIO IO PD VESD(HBM) Parameter Storage Temperature (VCC Off, Oscillator Off) Supply Voltage Lead Solder Temperature for 10 Seconds Input or Output Voltages Output Current Power Dissipation Electro-static discharge voltage (Human Body Model) TA = 25C TA = 25C Conditions(1) Value(2) -55 to 125 -0.3 to 5.0 260 -0.2 to Vcc+0.3 20 1 >1500 >1000 Unit C V C V mA W V V
VESD(RCDM) Electro-static discharge voltage (Robotic Charged Device Model)
1. Test conforms to JEDEC standard 2. Data based on characterization results, not tested in production
3. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds)
15/24
DC and AC parameters
M41T60
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 5. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M41T60 1.3V to 4.4V -40 to 85C 50pF 5ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 13. AC testing I/O waveform Figure 14. Crystal isolation example
Local Grounding Plane (Layer 2)
XI
0.8VCC
Crystal
0.7VCC 0.3VCC
AI02568
XO GND
0.2VCC
AI09127
Note:
Substrate pad should be tied to VSS. Table 6. Capacitance
Symbol CIN COUT(3) tLP Parameter (1)(2) Input Capacitance (SCL) Output Capacitance (SDA, OUT) Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
16/24
M41T60
DC and AC parameters
Table 7. DC Characteristics
Symbol VCC(2) ICC1 Parameter Operating Voltage Test Condition(1) Clock (3) I2C Bus (400kHz) Supply Current SCL = 400kHz (No Load) VCC = 4.4V VCC = 3.6V VCC = 3.0V VCC = 2.5V VCC = 2.0V ICC2 Supply Current (Standby) SCL = 0Hz All inputs VCC - 0.2V VSS + 0.2V 4.4V 3.6V 3.0V @ 25C 2.0V @ 25C VIL VIH VOL Input Low Voltage Input High Voltage Output Low Voltage VCC = 4.4V, IOL = 3mA (SDA) VCC = 4.4V, IOL = 1mA (OFIRQ/OUT) Pull-up Supply Voltage (Open Drain) ILI ILO Input Leakage Current Output Leakage Current FT, OFIRQ/OUT 0V VIN VCC 0V VOUT VCC -1.0 -1.0 -0.2 0.7 VCC 375 350 310 0.3 VCC VCC + 0.3 0.4 0.4 4.4 +1.0 +1.0 50 35 30 20 950 700 Min 1.0 1.3 Typ Max 4.4 4.4 100 70 Unit V V A A A A A nA nA nA nA V V V V V A A
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.3 to 4.4V (except where noted). 2. When using battery back-up, VCC fall time should not exceed 10mV/s. 3. Oscillator start-up guaranteed at 1.5V only.
Table 8. Crystal electrical characteristics
Symbol
fO
Parameter (1)(2) Resonant Frequency Series Resistance (TA = -40 to 70C, oscillator start-up at 2.0V) Load Capacitance
Min
Typ 32.768
Max
Unit kHz
RS CL
75 (3)(4) 6
k pF
1. These values are externally supplied. STMicroelectronics recommends the Citizen CFS-145 (1.5x5mm) and the KDS DT38 (3x8mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) for surface-mount, tuning fork-type quartz crystals. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. 2. Load capacitors are integrated within the M41T60. Circuit board layout considerations for the 32.768KHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design. 4. RS (max) = 65k for TA = -40 to 85C and oscillator start-up at 1.5V.
17/24
DC and AC parameters
M41T60
Table 9. Oscillator characteristics
Symbol
VSTA
Parameter Oscillator Start Voltage Oscillator Start Time XIN XOUT IC-to-IC Frequency Variation (1)
Conditions 10 seconds VCC = 3.0V
Min 1.5
Typ
Max
Unit V
tSTA Cg Cd
1 12 12 -10 +10
s pF pF ppm
1. Reference value. TA = 25C, VCC = 3.0V, CMJ-145 (CL = 6pF, 32,768Hz) manufactured by Citizen.
Figure 15. Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Note:
P = STOP and S = START Table 10. AC characteristics
Symbol fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT Parameter(1) SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Setup Time 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Unit kHz s ns ns ns ns ns ns s ns s
tHD:DAT(2) Data Hold Time tSU:STO tBUF STOP Condition Setup Time Time the bus must be free before a new transmission can start
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.3 to 4.4V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
18/24
M41T60
Package mechanical information
6
Package mechanical information
Figure 16. QFN16 - 16-lead, quad, flat package, no lead, 3x3mm body size, Outline
D
E
A3
A1
A
ddd C
b L
e K
1 2
E2
3
Ch
K D2
QFN16-A
Note:
Drawing is not to scale.
19/24
Package mechanical information
M41T60
Table 11. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data
mm Dim Typ A A1 A3 b D D2 E E2 e K L ddd Ch N 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 - - Min 0.80 0.00 - 0.18 2.90 1.55 2.90 1.55 - - 0.30 0.08 0.33 16 Max 1.00 0.05 - 0.30 3.10 1.80 3.10 1.80 - - 0.50 - - Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016 - - Min 0.032 0.000 - 0.007 0.114 0.061 0.114 0.061 - - 0.012 0.003 0.013 16 Max 0.039 0.002 - 0.012 0.122 0.071 0.122 0.071 - - 0.020 - - inches
Figure 17. QFN16, quad, flat package, no lead, 3x3mm, recommended footprint
Note:
Substrate pad should be tied to VSS.
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M41T60
Package mechanical information Figure 18. 32KHz Crystal + QFN16 vs. VSOJ20 mechanical data
7.0 0.3
VSOJ20
6.0 0.2 3.2
1
XI XO
SMT CRYSTAL
2 3 4
2.9
ST QFN16
1.5
Note: Dimensions shown are in millimeters (mm).
2.9
AI11146
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Part numbering
M41T60
7
Part numbering
Table 12. Ordering Information Scheme
Example: M41T 60 Q 6 F
Device Family M41T
Device Type and Supply Voltage 60 = VCC = 1.3 to 4.4V
Package Q = QFN16 (3mm x 3mm)
Temperature Range 6 = -40 to 85C
Shipping Method F = Lead-Free Package, Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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M41T60
Revision history
8
Revision history
Table 13. Revision history
Date 13-Nov-2003 20-Nov-2003 25-Dec-2003 13-Jan-2004 26-Feb-2004 02-Mar-2004 26-Apr-2004 13-May-2004 06-Aug-2004 25-Oct-2004 20-Dec-2004 05-May-2005 31-Oct-2005 30-Nov-2005 06-Jul-2006 Version 1.0 1.1 2.0 2.1 2.2 2.3 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 First Issue Update characteristics (Figure 2, 3, 4; Table 1, 2, 5, 7, 10) Reformatted; add crystal isolation, footprint (Figure 12) Update characteristics (Figure 9, 10, 12; Table 7, 12) Update characteristics and mechanical dimensions (Figure 14, 17; Table 4 , 7, 11) Update characteristics (Table 7) Reformat and republish Update characteristics (Table 7 , 7, 8; Figure 14 , 17) Update characteristics (Figure 2; Table 7, 9) Document Status Promotion; update characteristics (Figure 1; Table 4 ,7, 8, 9, 12) Corrected footprint; update characteristics (Figure 4, 17; Table 7 , 7) Add package comparison and mechanical data (Figure Figure 18) Update: bus operating voltage, characteristics (Figure 4; Table 4, 7, 10, 12) Update ESD:HBM rating, crystal characteristics (Table 4 , 8) New template Changes
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M41T60
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